1. Field of the Invention
The present disclosure relates to the field of fabricating microstructures, such as integrated circuits, and, more particularly, to a technique for controlling alignment accuracy and pattern placement precision during lithography processes in forming and patterning stacked material layers.
2. Description of the Related Art
The fabrication of microstructures, such as integrated circuits, requires tiny regions of precisely controlled size to be formed in a material layer of an appropriate substrate, such as a silicon substrate, a silicon-on-insulator (SOI) substrate or other suitable carrier materials. These tiny regions of precisely controlled size are generated by patterning the material layer by performing lithography, etch, implantation, deposition, oxidation processes and the like, wherein typically, at least in a certain stage of the patterning process, a mask layer may be formed over the material layer to be treated to define these tiny regions. Generally, a mask layer may consist of or may be formed by means of a layer of photoresist that is patterned by a lithographic process, typically a photolithography process. During the photolithography process, the resist may be spin-coated onto the substrate surface and then selectively exposed to ultraviolet radiation through a corresponding lithography mask, such as a reticle, thereby imaging the reticle pattern into resist layer to form a latent image therein. After developing the photoresist, depending on the type of resist, positive resist or negative resist, the exposed portions or the non-exposed portions are removed to form the required pattern in the layer of photoresist. Based on this resist pattern, actual device patterns may be formed by further manufacturing processes, such as etch, implantation, anneal processes and the like. Since the dimensions of the patterns in sophisticated integrated microstructure devices are steadily decreasing, the equipment used for patterning device features have to meet very stringent requirements with regard to resolution and overlay accuracy of the involved fabrication processes. In this respect, resolution is considered as a measure for specifying the consistent ability to print minimum size images under conditions of predefined manufacturing variations. One important factor in improving the resolution is the lithographic process, in which patterns contained in the photo mask or reticle are optically transferred to the substrate via an optical imaging system. Therefore, great efforts are made to steadily improve optical properties of the lithographic system, such as numerical aperture, depth of focus and wavelength of the light source used.
The quality of the lithographic imagery is extremely important in creating very small feature sizes. Of at least comparable importance is the accuracy with which an image can be positioned on the surface of the substrate. Typically, microstructures, such as integrated circuits, are fabricated by sequentially patterning material layers, wherein features on successive material layers bear a spatial relationship to one another. Each pattern formed in a subsequent material layer has to be aligned to a corresponding pattern formed in the previously patterned material layer within specified registration tolerances. These registration tolerances are caused by, for example, a variation of a photoresist image on the substrate due to non-uniformities in such parameters as resist thickness, baking temperature, exposure dose and time and development conditions. Furthermore, non-uniformities of the etch processes can also lead to variations of the etched features. In addition, there exists an uncertainty in overlaying the image of the pattern of the current material layer to the etched or otherwise defined pattern of the previously formed material layer while photolithographically transferring the image of the photo mask onto the substrate. Several factors contribute to an imperfect ability of the imaging system to overlay two layers, such as imperfections within a set of masks, temperature differences at the different times of exposure, a limited registration capability of the alignment tool and, as a major contribution to alignment errors, imperfections of the exposure tool itself, such as lens distortions, and distortions caused by the alignment hardware, such as the substrate holder, and the like. The situation becomes even worse when different exposure tools are used for defining subsequent device layers, since then the inherent errors in the exposure tool and related components may vary between the different tools.
Although the same exposure tool might be used for imaging critical device layers, in practice, such restrictions may not allow an efficient overall process flow in a complex manufacturing environment, which typically comprises a plurality of lithography tools for the same device layer. As a result, the dominant criteria for determining the minimum feature size that may finally be obtained are the resolution for creating features in individual substrate layers and the total overlay error to which the above-explained factors, in particular the lithographic process, contribute.
Therefore, it is essential to continuously monitor the resolution, i.e., the capability of reliably and reproducibly creating the minimum feature size, also referred to as critical dimension (CD), within a specific material layer, and to continuously determine the overlay accuracy of patterns of material layers that have been successively formed and that have to be aligned to each other. For example, when forming a wiring structure for an integrated circuit, respective metal lines and vias, which connect two stacked metal regions, may have to be aligned to each other with strict process margins, since a significant misalignment may cause a short between actually non-connected lines, thereby possibly creating a fatal device defect.
Thus, modern advanced process control (APC) strategies strive to reduce respective errors on the basis of the measurement results obtained from previously measured substrates, in order to feed back the mismatch indicated by the measurement data for reducing the alignment error in the next substrate to be processed. APC controllers may have a predictive behavior, which is typically referred to as model predictive control (MPC), which may be convenient when the amount of available measurement data is restricted due to process requirements.
For generating appropriate manipulated values, the measured “overlay” may be separated into individual alignment parameters, such as magnification, translation, substrate rotation, reticle rotation, orthogonality and the like. Consequently, a corresponding exposure tool recipe for aligning the image of a reticle with respect to a specified position of the substrate may contain respective manipulated variables that correspond to the overlay parameters specified above. The manipulated variables may represent so-called controller inputs, that is, any process parameters of the lithography tool which may be adjusted by the controller so as to obtain specified values for the above-specified overlay parameters or control variables, such as magnification, x-translation, orthogonality and the like.
For instance, in controlling the accurate pattern placement of two corresponding device layers, measurement results may be gathered from a stream of a specific number of substrate lots to calculate the alignment parameters, for instance ten alignment parameters of a linear alignment model, which may then be fed back to the lithography tool to expose the next substrate lot. In this way, drifts of the lithography tool or changes in the technology may be corrected. As previously discussed, high volume production lines for semiconductor devices may have to fulfill critical overlay specifications while at the same time reduce overall cycle time per mask layer. For this reason, advanced lithography tools, such as step and scanning tools, may have two substrate holders or chucks to provide alternating processing, i.e., while exposing one substrate, a further substrate is aligned and positioned in the other substrate holder. Since the characteristics of the substrate holders may also have a significant effect on the finally obtained alignment precision, and thus on the exposure of the substrates, respective overlay correction data, i.e., the corresponding linear alignment parameters, may be established separately for each substrate holder in order to enable different corrections for each of the substrate holders. Although significant improvements with respect to overall process accuracy may be achieved, in particular in sophisticated production lines, in which typically a plurality of lithography tools may be used, the degree of alignment accuracy may not be compatible with the quality specifications. Hence, very restrictive constraints may be imposed on the lithography processes, for instance by dedicating tools so that two subsequent critical mask layers may be imaged by the same lithography tool. Consequently, a reduced flexibility in substrate scheduling may occur, thereby contributing to a significant increase of overall cycle time, in particular in high volume production process lines.
The present disclosure is directed to various methods and systems that may avoid, or at least reduce, the effects of one or more of the problems identified above.